Integrated circuits are formed on wafers. Each wafer includes many patterned layers such as well regions, a polysilicon layer, metal layers, and the like. The alignment of the layers is referred to as an overlay control, which involves measuring the misalignment between two successive layers on the surface of a wafer. Generally, the minimization of misalignment errors is important to ensure that the multiple layers of the integrated circuit devices are connected. As advances in technology facilitate smaller critical dimensions for integrated circuit devices, the need for the reduction in misalignment errors increases significantly.
Generally, a set of photolithography steps is performed on a lot of wafers using a semiconductor manufacturing tool commonly referred to as an exposure tool, such as a stepper or a scanner. The manufacturing tool communicates with a manufacturing framework or a network of processing modules. The manufacturing tool is generally connected to an equipment interface. The equipment interface is further connected to a machine interface to which the stepper is connected, thereby facilitating communications between the stepper and the manufacturing framework. The machine interface may generally be a part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
A metrology tool may be used to measure the overlay errors in exposed wafers, and to feedback the overlay errors to the lithography process of subsequent wafers. However, abnormal cases may occur. For example, an error may occur to the metrology tool that is used to measure the overlay errors. This type of errors may be adversely propagated to the formation of subsequent wafers, causing the requirement of re-performing in the lithograph process of subsequent wafers or even the scrap of the subsequent wafers.